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Datasheet File OCR Text:

D at a S he e t, R ev . 0 .8 5 , Ap r . 2 00 4
H YS72 T 640 00 [G/H ]R - x -A (5 12 M B y t e ) H YS72 T 128 00 0[ G/H] R-x-A ( 1 G B y t e ) H YS72 T 128 02 0[ G/H] R-x-A ( 1 G B y t e ) H YS72 T 256 02 0[ G/H] R-x-A ( 2 G B y t e ) H YS72 T 256 22 0[ G/H] R-x-A ( 2 G B y t e )
DDR 2 Reg istered Me mo ry Mo dul es
M em or y P r od uc t s
Never stop thinking.
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Preliminary Data Sheet Rev. 0.85 (Apr. 2004) Low Profile 240-pin Registered DDR2 SDRAM Modules Datasheet 512 MByte, 1 GByte & 2 GByte Modules PC2-3200R, PC2-4300R
* 240-pin Registered 8-Byte ECC Dual-In-Line DDR2 SDRAM Module for PC, Workstation and Server main memory applications * One rank 64Mb x 72, 128Mb x 72 and two ranks 128Mb x 72 and 256Mb x 72 organizations * JEDEC standard Double Data Rate 2 Synchronous DRAMs (DDR2 SDRAMs) with + 1.8 V ( 0.1 V) power supply * 512MB and 1 GB modulesModules built with 512Mb DDR2 SDRAMs in 60-ball FBGA chipsize packages * Two versions of 2 GB modules
built with 63-ball FBGA dual die chipsize packages (2 x 512Mb components) or 60-ball FBGA packages Performance: Speed Grade Indicator Component Speed Grade on Module Module Speed Grade Max. Clock Frequency @ CL = 3 Max. Clock Frequency@ CL = 4 & 5 -5 DDR2-400 PC2-3200R 200 200 -3.7 DDR2-533 PC2-4300R 200 266 MHz MHz Unit
* Programmable CAS Latencies (3, 4 & 5), Burst Length (4 & 8) and Burst Type. * Auto Refresh and Self Refresh * All inputs and outputs SSTL_1.8 compatible * Re-drive for all input signals using register and PLL devices. * OCD (Off-Chip Driver Impedance Adjustment) and ODT (On-Die Termination) * Serial Presence Detect with E2PROM * Low Profile Modules form factor: 133.35 mm x 30,00 mm (MO-237) * Based on JEDEC standard reference card designs
1.0 Description The INFINEON HYS72Taaabcd[G/H]R module family are low profile Registered DIMM modules with 30,00 mm height based on DDR2 technology. DIMMs are available in 64M x 72 (512MByte), 128M x 72 (1GByte) and 256M x 72 (2GByte) organisation and density, intended for mounting into 240 pin connector sockets. The memory array is designed with 512Mb Double Data Rate (DDR2) Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. Decoupling capacitors are mounted on the PCB board, which provide a proper voltage supply impedance over the whole frequency range of operations as number and values are accordant to the JEDEC specification. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
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1.1 Ordering Information
Product Type PC2-3200 (DDR2-400) HYS72T64000GR-5-A HYS72T128020GR-5-A HYS72T128000GR-5-A HYS72T256220GR-5-A HYS72T256020GR-5-A PC2-4300 (DDR2-533) HYS72T64000GR-3.7-A HYS72T128020GR-3.7-A HYS72T128000GR-3.7-A HYS72T256020GR-3.7-A PC2-3200 (DDR2-400) HYS72T64000HR-5-A HYS72T128020HR-5-A HYS72T128000HR-5-A HYS72T256220HR-5-A HYS72T256020HR-5-A PC2-4300 (DDR2-533) HYS72T64000HR-3.7-A HYS72T128020HR-3.7-A HYS72T128000HR-3.7-A HYS72T256020HR-3.7-A PC2-4300R-444-11-A PC2-4300R-444-11-B PC2-4300R-444-11-C PC2-4300R-444-11 one rank 512 MB Reg. DIMM two ranks 1024 MB Reg.DIMM one rank 1024 MB Reg. DIMM two ranks 2048 MB Reg. DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x4) PC2-3200R-333-11-A PC2-3200R-333-11-B PC2-3200R-333-11-C PC2-3200R-333-11 PC2-3200R-333-11 one rank 512 MB Reg. DIMM two ranks 1024 MB Reg.DIMM one rank 1024 MB Reg. DIMM two ranks 2048 MB Reg. DIMM two ranks 2048 MB Reg. DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x4) 512 Mbit (x4) PC2-4300R-444-11-A PC2-4300R-444-11-B PC2-4300R-444-11-C PC2-4300R-444-11 one rank 512 MB Reg. DIMM two ranks 1024 MB Reg.DIMM one rank 1024 MB Reg. DIMM two ranks 2048 MB Reg. DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x4) PC2-3200R-333-11-A PC2-3200R-333-11-B PC2-3200R-333-11-C PC2-3200R-333-11 PC2-3200R-333-11 one rank 512 MB Reg. DIMM two ranks 1024 MB Reg.DIMM one rank 1024 MB Reg. DIMM two ranks 2048 MB Reg. DIMM two ranks 2048 MB Reg. DIMM 512 Mbit (x8) 512 Mbit (x8) 512 Mbit (x4) 512 Mbit (x4) 512 Mbit (x4) Compliance Code Description SDRAM Technology
Notes: 1. For all INFINEON DDR2 module and component nomenclature see section 8 of this data sheet. 2. The Compliance Code is printed on the module label and describes the speed grade, e. g. "PC2-4300R-444-11-C", where 4300R means Registered modules with 4.26 GB/sec Module Bandwidth and "444-11" means CAS latency = 4, trcd latency = 4 and trp latency = 4 using the latest JEDEC SPD Revision 1.1 and produced on the Raw Card "C".
1.2 Address Format
Product Type HYS72T64000GR HYS72T64000HR HYS72T128020GR HYS72T128020HR HYS72T128000GR HYS72T128000HR HYS72T256220GR HYS72T256220HR HYS72T256020GR HYS72T256020HR DIMM Density Organization DIMM Ranks SDRAMs # of SDRAMs # of row/bank/ column bits 512 MB 1024 MB 1024 MB 2048 MB 2048 MB 64Mb x 72 2 x 64Mb x 72 128Mb x 72 2 x 128Mb x 72 2 x 128Mb x 72 1 2 1 2 2 (512Mb) 64Mb x 8 (512Mb) 64Mb x 8 (512Mb) 128Mb x 4 (512Mb) 128Mb x 4 (512Mb) 128Mb x 4 9 18 18 36 36 14/2/10 14/2/10 14/2/11 14/2/11 14/2/11
Data Sheet Preliminary
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1.3 Components on Modules and RawCard
DIMM Density 512 MB 1024 MB 1024 MB 2048 MB 2048 MB DRAM components reference datasheet HYB18T512800AC HYB18T512800AF HYB18T512800AC HYB18T512800AF HYB18T512400AC HYB18T512400AF HYB18T512400AC HYB18T512400AF HYB18T512400AC HYB18T512400AF PLL 1:10, 1.8V, CU877 1:10, 1.8V, CU877 1:10, 1.8V, CU877 tbd. tbd. Register 1:1 25-bit 1.8V SSTU32864 1:2 14-bit 1.8V SSTU32864 1:2 14-bit 1.8V SSTU32864 tbd. tbd. Raw Card A B C tbd. tbd.
For a detailed description of all functionalities of the DRAM components on these modules see the referenced component data sheet
1.4 Pin Definition and Function
Pin Name A[13:0] A11, A[9:0] A10/AP BA[1:0] CK0 CK0 RAS CAS WE CS[1:0] CKE[1:0] ODT[1:0] DQ[63:0] Description Row Address Inputs Column Address Inputs 4) Column Address Input for AutoPrecharge SDRAM Bank Selects Clock input
(positive line of differential pair)
Pin Name CB[7:0] DQS[8:0] DM[8:0] / DQS[17:9] DQS[17:0] SCL SDA SA[2:0] VDD VREF VSS VDDSPD RESET NC
Description DIMM ECC Check Bits SDRAM low data strobes SDRAM low data mask/ high data strobes SDRAM differential data strobes Serial bus clock Serial bus data line slave address select Power (+ 1.8 V) I/O reference supply Ground EEPROM power supply Register and PLL control pin 2) No connection
Clock input
(negative line of differential pair)
Row Address Strobe Column Address Strobe Read/Write Input Chip Selects 3) Clock Enable 3) Active termination control lines 1) 3) Data Input/Output
1) Active termination only applies to DQ, DQS, DQS and DM signals 2) When low, all register outputs will be driven low and the PLL clocks to the DRAM and registers will be set to low levels (the PLL will remain synchronized with the input clock 3) CS1, ODT1 and CKE1 are used on dual rank modules only 4) Column address A11 is used on modules based on x4 organised 512Mb DDR2 components only.
Data Sheet Preliminary
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1.5 Pin Configuration
PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol VREF VSS DQ0 DQ1 VSS DQS0 DQS0 VSS DQ2 DQ3 VSS DQ8 DQ9 VSS DQS1 DQS1 VSS RESET NC VSS DQ10 DQ11 VSS DQ16 DQ17 VSS DQS2 DQS2 VSS DQ18 DQ19 VSS DQ24 DQ25 VSS DQS3 DQS3 VSS DQ26 DQ27 PIN# 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Symbol VSS DQ4 DQ5 VSS DM0, DQS9 DQS9 VSS DQ6 DQ7 VSS DQ12 DQ13 VSS DM1, DQS10 DQS10 VSS NC NC VSS DQ14 DQ15 VSS DQ20 DQ21 VSS DM2, DQS11 DQS11 VSS DQ22 DQ23 VSS DQ28 DQ29 VSS DM3, DQS12 DQS12 VSS DQ30 DQ31 VSS PIN# 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Symbol A4 VDDQ A2 VDD KEY VSS VSS VDD NC VDD A10/AP BA0 VDDQ WE CAS VDDQ CS1 ODT1 VDDQ VSS DQ32 DQ33 VSS DQS4 DQS4 VSS DQ34 DQ35 VSS DQ40 DQ41 VSS DQS5 DQS5 VSS DQ42 DQ43 VSS DQ48 DQ49 PIN# 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 Symbol VDDQ A3 A1 VDD KEY CK0 CK0 VDD A0 VDD BA1 VDDQ RAS CS0 VDDQ ODT0 A13 VDD VSS DQ36 DQ37 VSS DM4, DQS13 DQS13 VSS DQ38 DQ39 VSS DQ44 DQ45 VSS DM5, DQS14 DQS14 VSS DQ46 DQ47 VSS DQ52 DQ53 VSS
Data Sheet Preliminary
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Pin Configuration (cont'd)
PIN# 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
Symbol VSS CB0 CB1 VSS DQS8 DQS8 VSS CB2 CB3 VSS VDDQ CKE0 VDD NC NC VDDQ A11 A7 VDD A5
PIN# 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180
Symbol CB4 CB5 VSS DM8, DQS17 DQS17 VSS CB6 CB7 VSS VDDQ NC, CKE1 VDD NC NC VDDQ A12 A9 VDD A8 A6
PIN# 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
Symbol VSS SA2 NC VSS DQS6 DQS6 VSS DQ50 DQ51 VSS DQ56 DQ57 VSS DQS7 DQS7 VSS DQ58 DQ59 VSS SDA SCL
PIN# 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
Symbol NC NC VSS DM6, DQS15 DQS15 VSS DQ54 DQ55 VSS DQ60 DQ61 VSS DM7, DQS16 DQS16 VSS DQ62 DQ63 VSS VDDSPD SA0 SA1
1.6 Pin Locations
Front
p in 1 pin 1 21
64 18 4
65 1 85
120 2 40
Backside
240 pin Modules (MO-237)
Data Sheet Preliminary
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1.7 Registered DIMM Input/Output Functional Description
Symbol CK0, CK0 Type
Input
Polarity
Function
The system clock inputs. All address and command lines are sampled on the cross point of Cross point the rising edge of CK and the falling edge of CK. An on-board DLL circuit is driven from the clock inputs and output timing for read operations is synchronized to the input clock. CKE high activates and CKE low deactivates internal clock signals and device input buffers Active High and output drivers of the SDRAMs. Taking CKE low provides Precharge Power-Down and Self-Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is disabled, new commands are ignored and previous operations conActive Low tinue. The input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high. When both CS[1:0] are high, all register outputs (except CK, ODT and Chip select) remain in the previous state. Active High On-Die Termination control signals Active Low When sampled at the positive edge of the clock, RAS, CAS and WE define the operation to be executed by the SDRAM. Active High Masks write data when high, issued concurrently with input data. Selects which internal SDRAM memory bank is activated During Bank Activate command cycle, Address defines the row address. During a Read or Write command cycle, Address defines the column address. In addition to the column address, A10(=AP) is used to invoke Auto-Precharge operation at the end of the burst read or write cycle. If AP is high, Auto Precharge is selected and BA[1:0] defines the bank to be precharged. If AP is low, Auto-Precharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA[1:0] to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA[1:0]. If AP is low, BA[1:0] are used to define which bank to precharge. Data and Check Bit Input /Output pins.
CKE[1:0]
Input
CS[1:0]
Input
ODT[1:0] RAS, CAS, WE DM[8:0] BA[1:0]
Input Input Input Input
A[13:0]
Input
-
DQ[63:0], CB[7:0]
I/O
-
DQS[17:0], DQS[17:0]
I/O
The data strobes, associated with one data byte, source with data transfer. In Write mode, the data strobe is sourced by the controller and is centered in the data window. In Read mode the data strobe is sources by the DDR2 SDRAM and is sent at the leading edge of the Cross point data window. DQS signals are complements, and timing is relative to the crosspoint of respective DQS and DQS. If the module is to be operated in single ended strobe mode, all DQS signals must be tied on the system board to VSS and DDR2 SDRAM mode registers programmed appropriately. These signals are tied at the system planar to either VSS or VDDSPD to configure the serial SPD EEPROM address range This bidirectional pin is used to transfer data into and out of the SPD EEPROM. A resistor maybe connected from the SDA bus line to VDDSPD on the system planar to act as a pullup. This signal is used to clock data into the SPD EEPROM. A resistor maybe connected from the SCL bus line to VDDSPD on the system planar to act as a pull-up. The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and the register(s) will be set to low level. The PLL will remain synchronized with the input clock. Power and ground for the DDR SDRAM input buffers and core logic. Reference voltage for the SSTL-18 inputs. Serial EEPROM positive power supply, wired to a separated power pin at the connector which supports from 1.7 Volt to 3.6 Volt.
SA[2:0] SDA SCL RESET VDD, VSS VREF VDDSPD
Input I/O
Input Input Supply Supply Supply
Note: CS1, ODT1 and CKE1 are used on dual rank modules only.
Data Sheet Preliminary
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2.0 Block Diagrams 2.1 One Rank 64M x 72 (512 MByte) DDR2 SDRAM DIMM Module (x8 components) HYS72T64000[G/H] on Raw Card A
RS0 DQS0 DQS0 DM0/DQS9 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS0 DM2/DQS11 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM8/DQS17 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 1:1 CS0 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7
R E G I S T E R
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
DQS4 DQS4 DM4/DQS13 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D0
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D1
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D5
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D2
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D7
VDDSPD Serial PD SCL D8 WP A0 A1 A2 SDA VDD, V DDQ VREF V SS
Serial PD
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0 - D8 D0 - D8 D0 - D8
SA0 SA1 SA2
RS0 -> C S : SDRAMs D0-D8 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0 -D8 RA0 -RA 13-> A0 -A 13: SDR A Ms D0 -D 8 RR A S -> RAS : SD RAMs D0- D 8 RC AS -> C A S: SD RAMs D0-D8 RW E -> WE : SD RAMs D0-D8 RCK E0 -> CKE : SDR A D0-D8 RODT0 -> ODT 0: SDRAMs D0-D8
CK0
CK 0 P L L OE
PCK0-PCK6,PCK8,PCK9 PCK0-PCK6,PCK8,PCK9 PCK7-> CK : Register PCK7 > CK : Register
CK : SDRAMs D0-D8 CK : SDRAMs D0-D8
RESET
RST
Notes: 1. DQ-to-I/O wiring may be changed within a byte 2. Unless otherwise noted, resistor values are 22 Ohms
*) CS0 connects to DCS and VDD connects to CSR on the Registers
Data Sheet Preliminary
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Block Diagrams (cont'd) 2.2 128M x 72 (1GByte) two rank DDR2 SDRAM DIMM Modules (x8 components) HYS72T128020[G/H] on Raw Card B
RS1 RS0 DQS0 DQS0 DM0/DQS9 DQS9 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DQS1 DM1/DQS10 DQS10 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS0 DM2/DQS11 DQS11 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DQS3 DM3/DQS12 DQS12 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DQS8 DM0/DQS17 DQS17 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
DQS4 DQS4 DM4/DQS13 DQS13 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DQS5 DM5/DQS14 DQS14 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DQS6 DM6/DQS15 DQS15 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DQS7 DM7/DQS16 DQS16 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS NU/ RDQS DM/ RDQS CS DQS DQS
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D0
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D9
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D4
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D13
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D1
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D10
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D5
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D14
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D2
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D11
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D15
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D3
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D12
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D7
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
D16
VDDSPD
Serial PD
I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1:2
D8
I/O I/O I/O I/O I/O I/O I/O I/O
0 1 2 3 4 5 6 7
VDD, V DDQ D17 VREF V SS Serial PD SCL
D0 - D17 D0 - D17 D0 - D17
SDA WP A0 A1 A2
CS0 * CS1 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET PCK7 PCK 7
RS0 -> C S : SDRAMs D0-D8 RS1 -> C S : SDRAMs D9-D17 RB A0 -RBA1 -> B A 0-BA1 : SDRAMs D0-D17 RA0 -RA 13-> A0 -A 13: SDR A Ms D0-D17 RR A S -> RAS : SD RAMs D0-D17 RC AS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE :SDRAMs D0-D8 RCK E1 -> CKE :SDRAMs D9-D17 RODT0 -> ODT : SDRAMs D0-D8 RODT1 -> ODT : SDRAMs D9-D17
R E G I S T E R
SA0 SA1 SA2 CK 0 CK 0 P L L OE PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8,PCK9 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17
RESET
: PCK7 -> CK Register PCK7 > CK : Register
RST
DQ-to-I/O wiring may be changed within a byte DQ/DQS/DQS, adress and control resistors are 22 Ohms
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register. RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
Data Sheet Preliminary
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Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
Block Diagrams (cont'd) 2.3 One Rank 128M x 72 (1 GByte) DDR2 SDRAM DIMM Modules (x4 components)
HYS72T128000[G/H] on Raw Card C
VSS RS0 DQS0 DQS0
DM CS DQS DQS
DQS9 DQS9
DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQS1 DQS0
I/O 0 I/O 1 I/O 2 I/O 3
D0 DQS10 DQS10
DQ4 DQ5 DQ6 DQ7
I/O 0 I/O 1 I/O 2 I/O 3
D9
DM
CS DQS DQS
DM
CS DQS
DQS
DQ8 DQ9 DQ10 DQ11 DQS2 DQS2
I/O 0 I/O 1 I/O 2 I/O 3
D1 DQS11 DQS11
DQ12 DQ13 DQ14 DQ15
I/O 0 I/O 1 I/O 2 I/O 3
D10
DM
CS DQS DQS
DM
CS DQS
DQS
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3
I/O 0 I/O 1 I/O 2 I/O 3
D2 DQS12 DQS12
DQ20 DQ21 DQ22 DQ23
I/O 0 I/O 1 I/O 2 I/O 3
D11
DM
CS DQS DQS
DM
CS DQS
DQS
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4
I/O 0 I/O 1 I/O 2 I/O 3
D3
DQ28 DQ29 DQ30 DQ31 DQS13 DQS13
I/O 0 I/O 1 I/O 2 I/O 3
D12
DM
CS DQS DQS
DM
CS DQS
DQS
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5
I/O 0 I/O 1 I/O 2 I/O 3
D4 DQS14 DQS14
DQ36 DQ37 DQ38 DQ39
I/O 0 I/O 1 I/O 2 I/O 3
D13
DM
CS DQS DQS
DM
CS DQS
DQS
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6
I/O 0 I/O 1 I/O 2 I/O 3
D5 DQS15 DQS15
DQ44 DQ45 DQ46 DQ47
I/O 0 I/O 1 I/O 2 I/O 3
D14
DM
CS DQS DQS
DM
CS DQS
DQS
DQ48 DQ49 DQ50 DQ51 DQS7 DQS7
I/O 0 I/O 1 I/O 2 I/O 3
D6
DQ52 DQ53 DQ54 DQ55 DQS16 DQS16
I/O 0 I/O 1 I/O 2 I/O 3
D15
DM
CS DQS DQS
DM
CS DQS
DQS
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8
I/O 0 I/O 1 I/O 2 I/O 3
D7 DQS17 DQS17
DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3
D16
DM
CS DQS DQS
DM
CS DQS
DQS
CB0 CB1 CB2 CB3
I/O 0 I/O 1 I/O 2 I/O 3
D8
CB4 CB5 CB6 CB7 Serial PD
I/O 0 I/O 1 I/O 2 I/O 3
D17
VDDSPD SDA
Serial PD
1:2 CS0 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 ODT0 RESET PCK7 PCK 7
R E G I S T E R
RS0 -> C S : SDRAMs D0-D17 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs RA0 -RA 13-> A0 -A 13: SDR A Ms D0-D17 RR A S -> RAS : SD RAMs D0-D17 RC AS -> C A S: SD RAMs D0-D17 RW E -> WE : SD RAMs D0-D17 RCK E0 -> CKE :SDRAMs D0-D17 RODT0 -> ODT : SDRAMs D0-D17
SCL WP A0 A1 A2
VDD, V DDQ VREF
D0 - D17 D0 - D17 D0 - D17 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17
SA0 SA1 SA2
V SS
CK 0 CK 0
RST
P L L
PCK0-PCK6, PCK0-PCK6,
PCK8,PCK9 PCK8,PCK9
*) CS0 connects to DCS of Register 1 and CSR of Register 2, CSR of Register 1 and DCS of Register 2 connects to VDD **) RESET, PCK7 and PCK7 connet to both Registers. Other signals connect to one of two Registers.
RESET
OE
PCK7 -> CK : Register PCK7 > CK : Register
DQ-to-I/O wiring may be changed within per nibble Unless otherwise noted, resistor values are 22 Ohms
Data Sheet Preliminary
10
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
Block Diagrams (cont'd) 2.4 256M x 72 (2 GByte) two rank DDR2 SDRAM DIMM Modules (x4 components)
HYS72T256020[G/H] / HYS72T256220[G/H]
RS1 VSS RS0 DQS0 DQS0
DM CS DQS DQS DM CS DQS DQS
DQS9 DQS9
DM CS DQS DQS DM CS DQS DQS
DQ0 DQ1 DQ2 DQ3 DQS1 DQS1
I/O 0 I/O 1 I/O 2 I/O 3
D0-0
I/O 0 I/O 1 I/O 2 I/O 3
D0-1 DQS10 DQS10
DQ4 DQ5 DQ6 DQ7
I/O 0 I/O 1 I/O 2 I/O 3
D9-0
I/O 0 I/O 1 I/O 2 I/O 3
D9-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DQ8 DQ9 DQ10 DQ11 DQS2 DQS2
I/O 0 I/O 1 I/O 2 I/O 3
D1-0
I/O 0 I/O 1 I/O 2 I/O 3
D1-1 DQS11 DQS11
DQ12 DQ13 DQ14 DQ15
I/O 0 I/O 1 I/O 2 I/O 3
D10-0
I/O 0 I/O 1 I/O 2 I/O 3
D10-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DQ16 DQ17 DQ18 DQ19 DQS3 DQS3
I/O 0 I/O 1 I/O 2 I/O 3
D2-0
I/O 0 I/O 1 I/O 2 I/O 3
D2-1 DQS12 DQS12
DQ20 DQ21 DQ22 DQ23
I/O 0 I/O 1 I/O 2 I/O 3
D11-0
I/O 0 I/O 1 I/O 2 I/O 3
D11-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DQ24 DQ25 DQ26 DQ27 DQS4 DQS4
I/O 0 I/O 1 I/O 2 I/O 3
D3-0
I/O 0 I/O 1 I/O 2 I/O 3
D3-1 DQS13 DQS13
DQ28 DQ29 DQ30 DQ31
I/O 0 I/O 1 I/O 2 I/O 3
D12-0
I/O 0 I/O 1 I/O 2 I/O 3
D12-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS DQS
DQ32 DQ33 DQ34 DQ35 DQS5 DQS5
I/O 0 I/O 1 I/O 2 I/O 3
D4-0
I/O 0 I/O 1 I/O 2 I/O 3
D4-1 DQS14 DQS14
DQ36 DQ37 DQ38 DQ39
I/O 0 I/O 1 I/O 2 I/O 3
D13-0
I/O 0 I/O 1 I/O 2 I/O 3
D13-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS DQS
DQ40 DQ41 DQ42 DQ43 DQS6 DQS6
I/O 0 I/O 1 I/O 2 I/O 3
D5-0
I/O 0 I/O 1 I/O 2 I/O 3
D5-1 DQS15 DQS15
DQ44 DQ45 DQ46 DQ47
I/O 0 I/O 1 I/O 2 I/O 3
D14-0
I/O 0 I/O 1 I/O 2 I/O 3
D14-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DQ48 DQ49 DQ50 DQ51 DQS7 DQS7
I/O 0 I/O 1 I/O 2 I/O 3
D6-0
I/O 0 I/O 1 I/O 2 I/O 3
D6-1 DQS16 DQS16
DQ52 DQ53 DQ54 DQ55
I/O 0 I/O 1 I/O 2 I/O 3
D15-0
I/O 0 I/O 1 I/O 2 I/O 3
D15-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DQ56 DQ57 DQ58 DQ59 DQS8 DQS8
I/O 0 I/O 1 I/O 2 I/O 3
D7-0
I/O 0 I/O 1 I/O 2 I/O 3
D7-1 DQS17 DQS17
DQ60 DQ61 DQ62 DQ63
I/O 0 I/O 1 I/O 2 I/O 3
D16-0
I/O 0 I/O 1 I/O 2 I/O 3
D16-1
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
DM CS DQS
DQS
CB0 CB1 CB2 CB3
I/O 0 I/O 1 I/O 2 I/O 3
D8-0
I/O 0 I/O 1 I/O 2 I/O 3
D8-1
CB4 CB5 CB6 CB7 Serial PD
I/O 0 I/O 1 I/O 2 I/O 3
D17-0
I/O 0 I/O 1 I/O 2 I/O 3 VDDSPD
D17-1 Serial PD
1:2 CS0 * CS1 * B A 0-BA1 A0 -A13 RAS CAS WE CKE0 CKE1 ODT0 ODT1 RESET PCK7 PCK 7
R E G I S T E R
RS0 -> C S : SDRAMs D0-0 ~ D17-0 RS1 -> C S : SDRAMs D0-1 ~ D17-1 RB A0 -RBA1 -> BA 0-BA1 : SDRAMs D0~D17 RA0 -RA 13-> A0 -A 13: SDR A Ms D0~D17 RR A S -> RAS : SD RAMs D0~D17 RC AS -> C A S: SDRAMs D0~D17 RW E -> WE : SDRAMs D0~D17 RCK E0 -> CKE : SDRAMs D0-0 ~ D17-0 RCK E1 -> CKE :SDRAMs D0-1 ~ D17-1 RODT0 -> ODT : SDRAMs D0-0 ~ D17-0 RODT1 -> ODT : SDRAMs D0-1 ~ D17-1
SCL WP A0 A1 A2
SDA VDD, V DDQ VREF SA0 SA1 SA2 CK 0 CK 0 P L L
OE
D0 - D17 D0 - D17 D0 - D17 CK : SDRAMs D0-D17 CK : SDRAMs D0-D17
V SS PCK0-PCK6, PCK8,PCK9 PCK0-PCK6, PCK8,PCK9
RESET
PCK7 -> CK : Register PCK7 > CK : Register
RST
Notes: 1. DQ-to-I/O wiring may be changed within a nibble. 2. Unless otherwise noted, resistors values are 22 Ohms
*) CS0 connects to CRS, CS1 connects to CSR on a Register. CS1 connects to DCS and CS0 connects to CSR on another Register. RESET, PCK7 and PCK7 connect to bother Registers. Other signals connect to one of two Registers.
Data Sheet Preliminary
11
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
3.0 Absolute Maximum Ratings
Parameter Symbol Limit Values min. Voltage on any pins relative to VSS Voltage on VDD relative to VSS Voltage on VDD Q relative to VSS Storage temperature range VIN, VOUT VDD VDDQ TSTG - 0.5 - 1.0 - 0.5 -55 max. 2.3 2.3 2.3 +100
o
Unit
V V
C
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3.1 Operating Temperature Range
Parameter Symbol Limit Values min. DIMM Module Operating Temperature Range (ambient) DRAM Component Case Temperature Range TOPR TCASE 0 0 max. +55 +95
o o
Unit
Notes
C C 1-4
1. DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs. For measurement conditions, please refer to the JEDEC document JESD51-2. 2. Within the DRAM Component Case Temperature range all DRAM specification will be supported. 3. Above 85oC DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 s. 4. Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85oC case temperature before initiating self-refresh operation.
3.2 Supply Voltage Levels and DC Operating Conditions
Parameter Symbol min. Device Supply Voltage Output Supply Voltage Input Reference Voltage EEPROM Supply Voltage DC Input Logic High DC Input Logic Low In / Output Leakage Current
1 2 3
Limit Values nom. 1.8 1.8 0.5 x VDDQ - - - - max. 1.9 1.9 0.51 x VDDQ 3.6 VDDQ + 0.3 VREF - 0.125 5
Unit
Notes
VDD VDDQ VREF VDDSPD VIH (DC) VIL (DC) IL
1.7 1.7 0.49 x VDDQ 1.7 VREF + 0.125 - 0.30 -5
V V V V V V A
1) 2)
3)
Under all conditions, VDDQ must be less than or equal to VDD Peak to peak AC noise on VREF may not exceed 2% VREF (DC).VREF is also expected to track noise variations in VDDQ. For any pin on the DIMM connector under test input of 0 V VIN VDDQ + 0.3 V.
Data Sheet Preliminary
12
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
4.0 IDD Specifications and Conditions 4.1 512 MByte Registered Module HYS72T64000[G/H] (one rank, nine components x8)
512 MByte HYS72T64000[G/H] Symbol Parameter / Condition Operating Current IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current Active PD Standby Current LP Active PD Standby Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
PC2-3200R "-5" max. 745 790 286 538 475 367 295 565 880 925 1330 304 36 1420
PC2-4300R "-3.7" max. 918 1008 369 639 603 477 378 693 1143 1188 1503 387 36 1593 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL.
4.2 1024 MByte Registered Module HYS72T128020[G/H] (two ranks, 18 components x8)
1024 MByte HYS72T128020[G/H] Symbol Parameter / Condition Operating Current IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current Active PD Standby Current LP Active PD Standby Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
PC2-3200R "-5" max. 899 944 440 944 818 602 458 998 1034 1079 1484 476 72 1574
PC2-4300R "-3.7" max. 1111 1201 562 1210 1030 778 580 1210 1336 1381 1696 598 72 1786 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note
1, 2 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2 1, 2 1, 2 1, 3 1, 3 1, 2
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
Data Sheet Preliminary
13
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
4.3 1024 Mbyte Registered Module HYS72T128000[G/H] (one rank, 18 components x4)
1024 MByte HYS72T128000[G/H] Symbol Parameter / Condition Operating Current IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current Active PD Standby Current LP Active PD Standby Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
PC2-3200R "-5" max. 1358 1448 440 944 818 602 458 998 1628 1718 2528 476 72 2708
PC2-4300R "-3.7" max. 1660 1840 562 1210 1030 778 580 1210 2110 2200 2830 598 72 3010 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Note: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL.
4.4 2048 MByte Registered Module HYS72T256[0/2]20[G/H] (two ranks, 36 components x4)
2048 MByte HYS72T256020[G/H] 2048 MByte HYS72T256220[G/H] Symbol Parameter / Condition Operating Current IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6 IDD7
Operating Current Precharge PD Standby Current Precharge Standby Current Precharge Quiet Standby Current Active PD Standby Current LP Active PD Standby Current Active Standby Current Operating Current Burst Read Operating Current Burst Write Auto-Refresh Current (tRFCmin.) Auto-Refresh Current (tREFI) Self-Refresh Current Operating Current
PC2-3200R "-5" max. 1394 1520 512 1520 1268 836 548 1628 1700 1790 2600 584 144 2780
PC2-4300R "-3.7" max. 1696 1912 623 1930 1570 1066 670 1930 2182 2272 2902 706 144 3082 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA Note
1, 2 1, 2 1, 3 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2 1, 2 1, 2 1, 3 1, 3 1, 2
Notes: 1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7 are defined with the outputs disabled. Currents includes Registers and PLL. 2) The other rank is in IDD2P Precharge Power-Down Standby Current mode 3) Both ranks are in the same IDD current mode
Data Sheet Preliminary
14
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
4.5 IDD Measurement Conditions
(VDD = 1.8V 0.1V; VDDQ = 1.8V 0.1V)
Symbol Parameter/Condition Operating Current - One bank Active - Precharge tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin., CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Operating Current - One bank Active - Read - Precharge IOUT = 0 mA, BL = 4, tCK = tCKmin., tRC = tRCmin., tRAS = tRASmin.,tRCD = tRCDmin.,AL = 0, CL = CLmin.; CKE is HIGH, CS is high between valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING. Precharge Power-Down Current: All banks idle; CKE is LOW; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD0 IDD1 IDD2P IDD2N IDD2Q IDD3P(0) IDD3P(1) IDD3N IDD4R IDD4W IDD5B IDD5D IDD6
Precharge Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
Precharge Quiet Standby Current: All banks idle; CS is HIGH; CKE is HIGH; tCK = tCKmin.;
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
inputs are FLOATING. inputs are FLOATING.
Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus MRS A12 bit is set to "0" (Fast Power-down Exit); Active Power-Down Current: All banks open; tCK = tCKmin., CKE is LOW; Other control and address inputs are STABLE, Data bus MRS A12 bit is set to "1" (Slow Power-down Exit); Active Standby Current: All banks open; tCK = tCKmin.; tRAS = tRASmax; tRP = tRPmin.,CKE is HIGH; CS is high between valid commands. Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Operating Current - Burst Read: All banks open; Continuous burst reads; BL = 4;AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands. Address inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0mA. Operating Current - Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLmin.; tCK = tCKmin.; tRAS = tRASmax., tRP = tRPmin.; CKE is HIGH, CS is high between valid commands.
Address inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tRFCmin. interval, CKE is HIGH, CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Distributed Auto-Refresh Current: tCK = tCKmin., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING. Self-Refresh Current: CKE 0.2V; external clock off, CK and CK at 0V; Other control and address inputs are FLOATING, Data bus inputs are FLOATING. RESET = Low. IDD6 current values are guaranteed up to TCASE of 85oC max. All Bank Interleave Read Current: 1. All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control and address bus inputs are STABLE during DESELECTS. Iout = 0mA. 2. Timing pattern: - DDR2 -400: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D - DDR2 -533: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D - DDR2 -667: A0 RA0 D D A1 RA1 D D A2 RA2 D D A3 RA3 D D D D D 3. Legend: A = Activate, RA = Read with Auto-Precharge, D=DESELECT
IDD7
Notes: 1. IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled. 2. Definitions for IDD: LOW is defined as VIN <= VIL(ac)max; HIGH is defined as VIN >= VIH(ac)min. STABLE is defined as inputs are stable at a HIGH or LOW level. FLOATING is defined as inputs are VREF = VDDQ / 2. SWITCHING is defined as: inputs are changing between HIGH and LOW every other clock (once per two cycles) for address and control signals, and inputs changing between HIGH and LOW every other clock (once per cycle) for DQ signals not including mask or strobes. 3. IDD1, IDD4R, and IDD7 current measurements are defined with the outputs disabled (Iout = 0 mA). To achieve this on module level the output buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH. 3. For two rank modules: For all active current measurements the other rank is in Precharge Power-Down Mode IDD2P 4. RESET signal is high for all currents, except for IDD6 "Self Refresh". 5. All current measurements includes Register and PLL current consumption.
Data Sheet Preliminary
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Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
4.5 IDD Measurement Conditions (cont'd)
For testing the IDD parameters, the following timing parameters are used:
PC2-3200R "-5" Parameter CAS Latency Clock Cycle Time Active to Read or Write delay Active to Active / Auto-Refresh command period Active bank A to Active bank B command delay Active to Precharge Command Precharge Command Period Auto-Refresh to Active / Auto-Refresh command period Average periodic Refresh interval x4 & x8 Symbol 3-3-3 CLmin tCKmin tRCDmin tRCmin tRRDmin tRASmin tRPmin tRFCmin tREFI 3 5 15 60 7.5 45 15 105 7.8 4-4-4 4 3.75 15 60 7.5 45 15 105 7.8 tCK ns ns ns ns ns ns ns s PC2-4300R "-3.7" Unit
4.6 ODT (On Die Termination) Current
The ODT function adds additional current consumption to the DDR2 SDRAM when enabled by the EMRS(1). Depending on address bits A6 & A2 in the EMRS(1) a "week" or "strong" termination can be selected. The current consumption for any terminated input pin, depends on the input pin is in tri-state or driving "0" or "1", as long a ODT is enabled during a given period of time.
ODT current per terminated pin:
EMRS(1) State min. typ. max. Enabled ODT current per DQ added IDDQ current for ODT enabled; ODT is HIGH; Data Bus inputs are FLOATING A6 = 0, A2 = 1 IODTO A6 = 1, A2 = 0 A6 = 0, A2 = 1 A6 = 1, A2 = 0 2.5 10 5 3 12 6 3.75 mA/DQ 15 7.5 mA/DQ mA/DQ 5 6 7.5 Unit mA/DQ
Active ODT current per DQ IODTT added IDDQ current for ODT enabled; ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING.
note: For power consumption calculations the ODT duty cycle has to be taken into account
Data Sheet Preliminary
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Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
5.0 Electrical Characteristics & AC Timings
5.1 AC Timing Parameter by Speed Grade (Component level data, for reference only) -5 DDR2-400
Min Max + 600 + 500 0.55 0.55 - 600 - 500 0.45 0.45
Symbol
Parameter
-3.7 DDR2-533
Min -500 -450 0.45 0.45 Max +500 +450 0.55 0.55
Unit
tAC tCH tCL tHP tCK tIS tIH tDS tDH tIPW tDIPW tHZ
DQ output access time from CK / CK
ps ps tCK tCK
tDQSCK DQS output access time from CK / CK
CK, CK high-level width CK, CK low-level width Clock Half Period Clock cycle time CL = 3 CL = 4 & 5
min. (tCL, tCH) 5000 5000 600 600 400 400 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 350 450
min. (tCL, tCH) 5000 3750 600 600 350 350 0.6 0.35 2*tACmin tACmin 8000 8000 tACmax tACmax tACmax 300 400 ps ps ps ps ps ps tCK tCK ps ps ps ps ps
Address and control input setup time Address and control input hold time DQ and DM input setup time DQ and DM input hold time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK / CK
tLZ(DQ) DQ low-impedance from CK / CK tLZ(DQS) DQS low-impedance from CK / CK tDQSQ tQHS tQH tDQSS
DQS-DQ skew (for DQS & associated DQ signals) Data hold skew factor Data Output hold time from DQS Write command to 1st DQS latching transition
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 70000 -
tHP-tQHS
WL -0.25 0.35 0.2 0.2 2 0.25 0.40 0.9 0.40 45 60 105
WL +0.25 0.60 1.1 0.60 70000 tCK tCK tCK tCK tCK tCK tCK tCK tCK ns ns ns
tDQSL,H DQS input low (high) pulse width (write cycle) tDSS tDSH tMRD tWPRE tWPST tRPRE tRPST tRAS tRC tRFC
DQS falling edge to CLK setup time (write cycle) DQS falling edge hold time from CLK (write cycle) Mode register set command cycle time Write preamble Write postamble Read preamble Read postamble Active to Precharge command Active to Active/Auto-refresh command period Auto-refresh to Active/Auto-refresh command period
Data Sheet Preliminary
17
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
Symbol
Parameter
-5 DDR2-400
Min Max 12 7.8 3.9
-3.7 DDR2-533
Min 15 15 7.5 2 15 WR+tRP 7.5 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH Max 12 7.8 3.9
Unit
tRCD tRP tRRD tCCD tWR tDAL tWTR tRTP tXARD tXARDS tXP tXSRD tXSNR tCKE tOIT
Active to Read or Write delay (with and without Auto-Precharge) delay Precharge command period Active bank A to Active bank B command CAS A to CAS B Command Period Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay Exit power down to any valid command (other than NOP or Deselect) Exit active power-down mode to read command (slew exit, lower power) Exit precharge power-down to any valid command (other than NOP or Deselect) Exit Self-Refresh to read command Exit Self-Refresh to non-read command CKE minimum high and low pulse width OCD drive mode output delay x4 & x8 (1k page size)
15 15 7.5 2 15 WR+tRP 10 7.5 2 6 - AL 2 200 tRFC + 10 3 0 tIS+tCK +tIH -
ns ns ns tCK ns tCK ns ns tCK tCK tCK tCK ns tCK ns ns s
tDELAY Minimum time clocks remain ON after CKE asynchronously drops low tREFI
Average Periodic Refresh Interval 0 C - 85 C 85oC - 95oC
o o
1. For details and notes see the relevant INFINEON component datasheet 2. Timing definition and values for tis, tih, tds and tdh may change due to actual JEDEC work. This may also effect the SPD code for these parameters.
5.2 ODT AC Electrical Characteristics and Operating Conditions (all speed bins)
Symbol Parameter / Condition min. 2 DDR2-400/533 DDR2-667 tAC(min) tAC(min) tAC(min) + 2 ns 2.5 tAC(min) tAC(min) + 2 ns 3 8 max. 2 tAC(max) + 1 ns tAC(max) + 0.7 ns 2 tCK + tAC(max) + 1 ns 2.5 tAC(max) + 0.6 ns 2.5 tCK + tAC(max) + 1 ns Units
tAOND tAON
ODT turn-on delay ODT turn-on
tCK ns ns tCK ns ns tCK tCK
tAONPD ODT turn-on (Power-Down Modes) tAOFD tAOF tAOFPD tANPD tAXPD
ODT turn-off delay ODT turn-off ODT turn-off delay (Power-Down Modes) ODT to Power Down Mode Entry Latency ODT Power Down Exit Latency
Data Sheet Preliminary
18
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
6.0 Serial Presence Detect Codes for Registered Modules 6.1 SPD Codes for PC2-4300R (-3.7) HYS72T256020GR-3.7-A HYS72T256020HR-3.7-A HYS72T128000GR-3.7-A HYS72T128000HR-3.7-A HYS72T128020GR-3.7-A HYS72T128020HR-3.7-A HYS72T64000GR-3.7-A HYS72T64000HR-3.7-A Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 04 01 3D 50 50 60 3C 1E Product Type
Organization
Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level 9 tCK @ CLmax (Byte 18) [ns] 10 tAC SDRAM @ CLmax (Byte 18) [ns] 11 Error Correction Support (non-ECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 Not used 20 DIMM Type Information 21 DIMM Attributes 22 Component Attributes 23 tCK @ CLmax -1 (Byte 18) [ns] 24 tAC SDRAM @ CLmax -1 [ns] 25 tCK @ CLmax -2 (Byte 18) [ns] 26 tAC SDRAM @ CLmax -2 [ns] 27 tRP.min [ns] 28 tRRD.min [ns]
2 GByte 1 GByte x72 x72 2 Ranks (x4) 1 Rank (x4) PC2-4300R-444 Rev. 1.1 Rev. 1.1 HEX HEX 80 80 08 08 08 08 0E 0E 0B 0B 61 60 48 48 00 00 05 05 3D 3D 50 50 02 02 82 82 04 04 04 04 00 00 0C 0C 04 04 38 38 00 00 01 01 07 05 01 01 3D 3D 50 50 50 50 60 60 3C 3C 1E 1E
1 GByte 512 MB x72 x72 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 3D 50 02 82 08 08 00 0C 04 38 00 01 05 01 3D 50 50 60 3C 1E
Data Sheet Preliminary
19
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-3.7-A HYS72T256020HR-3.7-A
HYS72T128000GR-3.7-A HYS72T128000HR-3.7-A
HYS72T128020GR-3.7-A HYS72T128020HR-3.7-A
Organization
Label Code Jedec SPD Revision Byte# Description 29 tRCD.min [ns] 30 tRAS.min [ns] 31 Module Density per Rank 32 tAS.min and tCS.min [ns] 33 tAH.min and tCH.min [ns] 34 tDS.min [ns] 35 tDH.min [ns] 36 tWR.min [ns] 37 tWTR.min [ns] 38 tRTP.min [ns] 39 Analysis Characteristics 40 tRC and tRFC Extension 41 tRC.min [ns] 42 tRFC.min [ns] 43 tCK.max [ns] 44 tDQSQ.max [ns] 45 tQHS.max [ns] 46 PLL Relock Time 47 TCASE.max Delta / T4R4W Delta 48 Psi(T-A) DRAM 49 T0 50 T2N (UDIMM) or T2Q (RDIMM) 51 T2P 52 T3N 53 T3P.fast 54 T3P.slow 55 T4R / T4R4W Sign 56 T5B 57 T7 58 Psi(ca) PLL 59 Psi(ca) REG 60 TPLL
2 GByte 1 GByte x72 x72 2 Ranks (x4) 1 Rank (x4) PC2-4300R-444 Rev. 1.1 Rev. 1.1 HEX HEX 3C 3C 2D 2D 01 01 25 25 37 37 10 10 22 22 3C 3C 1E 1E 1E 1E 00 00 00 00 3C 3C 69 69 80 80 1E 1E 28 28 0F 0F 51 51 78 78 3E 3E 22 22 1E 1E 1E 1E 24 24 17 17 34 34 1E 1E 20 20 C4 C4 8C 8C 61 61
1 GByte 512 MB x72 x72 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3E 22 1E 1E 24 17 34 1E 20 C4 8C 61 Rev. 1.1 HEX 3C 2D 80 25 37 10 22 3C 1E 1E 00 00 3C 69 80 1E 28 0F 51 78 3E 22 1E 1E 24 17 34 1E 20 C4 8C 61
Data Sheet Preliminary
20
Rev. 0.85, 2004-04
HYS72T64000GR-3.7-A HYS72T64000HR-3.7-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-3.7-A HYS72T256020HR-3.7-A
HYS72T128000GR-3.7-A HYS72T128000HR-3.7-A
HYS72T128020GR-3.7-A HYS72T128020HR-3.7-A
Organization
Label Code Jedec SPD Revision Byte# Description 61 TREG / Toggle Rate 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon (1) 65 JEDEC ID Code of Infineon (2) 66 JEDEC ID Code of Infineon (3) 67 JEDEC ID Code of Infineon (4) 68 JEDEC ID Code of Infineon (5) 69 JEDEC ID Code of Infineon (6) 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, Char 13 86 Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code 92 Test Program Revision Code
2 GByte 1 GByte x72 x72 2 Ranks (x4) 1 Rank (x4) PC2-4300R-444 Rev. 1.1 Rev. 1.1 HEX HEX 78 78 11 11 8E 8B C1 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xx xx 37 37 32 32 54 54 32 31 35 32 36 38 30 30 32 30 30 30 47 / 48 47 / 48 52 52 33 33 2E 2E 37 37 41 41 20 20 20 20 20 20 0x 2x xx xx
1 GByte 512 MB x72 x72 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 78 11 12 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 32 30 47 / 48 52 33 2E 37 41 20 20 20 2x xx Rev. 1.1 HEX 78 11 10 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 30 47 / 48 52 33 2E 37 41 20 20 20 20 2x xx
Data Sheet Preliminary
21
Rev. 0.85, 2004-04
HYS72T64000GR-3.7-A HYS72T64000HR-3.7-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-3.7-A HYS72T256020HR-3.7-A
HYS72T128000GR-3.7-A HYS72T128000HR-3.7-A
HYS72T128020GR-3.7-A HYS72T128020HR-3.7-A
Organization
Label Code Jedec SPD Revision Byte# Description 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 Not used 127
2 GByte 1 GByte x72 x72 2 Ranks (x4) 1 Rank (x4) PC2-4300R-444 Rev. 1.1 Rev. 1.1 HEX HEX xx xx xx xx xx xx xx xx xx xx xx xx 00 00
1 GByte 512 MB x72 x72 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX xx xx xx xx xx xx 00 Rev. 1.1 HEX xx xx xx xx xx xx 00
Data Sheet Preliminary
22
Rev. 0.85, 2004-04
HYS72T64000GR-3.7-A HYS72T64000HR-3.7-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
6.2 SPD Codes for PC2-3200R (-5) HYS72T256020GR-5-A HYS72T256020HR-5-A HYS72T256220GR-5-A HYS72T256220HR-5-A HYS72T128000GR-5-A HYS72T128000HR-5-A HYS72T128020GR-5-A HYS72T128020HR-5-A HYS72T64000GR-5-A HYS72T64000HR-5-A Rev. 1.1 HEX 80 08 08 0E 0A 60 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 04 01 50 60 50 60 Product Type
Organization
Label Code Jedec SPD Revision Byte# Description 0 Programmed SPD Bytes in EEPROM 1 Total number of Bytes in EEPROM 2 Memory Type (DDR2) 3 Number of Row Addresses 4 Number of Column Addresses 5 DIMM Rank and Stacking Information 6 Data Width 7 Not used 8 Interface Voltage Level 9 tCK @ CLmax (Byte 18) [ns] 10 tAC SDRAM @ CLmax (Byte 18) [ns] 11 Error Correction Support (nonECC, ECC) 12 Refresh Rate and Type 13 Primary SDRAM Width 14 Error Checking SDRAM Width 15 Not used 16 Burst Length Supported 17 Number of Banks on SDRAM Device 18 Supported CAS Latencies 19 Not used 20 DIMM Type Information 21 DIMM Attributes 22 Component Attributes 23 tCK @ CLmax -1 (Byte 18) [ns] 24 tAC SDRAM @ CLmax -1 [ns] 25 tCK @ CLmax -2 (Byte 18) [ns] 26 tAC SDRAM @ CLmax -2 [ns]
2 GByte 2 GByte x72 x72 2 Ranks (x4) 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 Rev. 1.1 HEX HEX 80 80 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 07 01 50 60 50 60 08 08 0E 0B 61 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 07 01 50 60 50 60
1 GByte 1 GByte 512 MB x72 x72 x72 1 Rank (x4) 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 80 08 08 0E 0B 60 48 00 05 50 60 02 82 04 04 00 0C 04 38 00 01 05 01 50 60 50 60 Rev. 1.1 HEX 80 08 08 0E 0A 61 48 00 05 50 60 02 82 08 08 00 0C 04 38 00 01 05 01 50 60 50 60
Data Sheet Preliminary
23
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-5-A HYS72T256020HR-5-A
HYS72T256220GR-5-A HYS72T256220HR-5-A
HYS72T128000GR-5-A HYS72T128000HR-5-A
HYS72T128020GR-5-A HYS72T128020HR-5-A
Organization
Label Code Jedec SPD Revision Byte# Description 27 tRP.min [ns] 28 tRRD.min [ns] 29 tRCD.min [ns] 30 tRAS.min [ns] 31 Module Density per Rank 32 tAS.min and tCS.min [ns] 33 tAH.min and tCH.min [ns] 34 tDS.min [ns] 35 tDH.min [ns] 36 tWR.min [ns] 37 tWTR.min [ns] 38 tRTP.min [ns] 39 Analysis Characteristics 40 tRC and tRFC Extension 41 tRC.min [ns] 42 tRFC.min [ns] 43 tCK.max [ns] 44 tDQSQ.max [ns] 45 tQHS.max [ns] 46 PLL Relock Time 47 TCASE.max Delta / T4R4W Delta 48 Psi(T-A) DRAM 49 T0 50 T2N (UDIMM) or T2Q (RDIMM) 51 T2P 52 T3N 53 T3P.fast 54 T3P.slow 55 T4R / T4R4W Sign 56 T5B 57 T7 58 Psi(ca) PLL
2 GByte 2 GByte x72 x72 2 Ranks (x4) 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 Rev. 1.1 HEX HEX 3C 3C 1E 1E 3C 3C 2D 2D 01 01 35 35 47 47 15 15 27 27 3C 3C 28 28 1E 1E 00 00 00 00 3C 3C 69 69 80 80 23 23 2D 2D 0F 0F 51 51 78 78 32 32 1D 1D 1E 1B 1E 17 28 1B 1E C4 1E 1B 1E 17 28 1B 1E C4
1 GByte 1 GByte 512 MB x72 x72 x72 1 Rank (x4) 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 3C 1E 3C 2D 01 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 1B 1E C4 Rev. 1.1 HEX 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 1B 1E C4 Rev. 1.1 HEX 3C 1E 3C 2D 80 35 47 15 27 3C 28 1E 00 00 3C 69 80 23 2D 0F 51 78 32 1D 1E 1B 1E 17 28 1B 1E C4
Data Sheet Preliminary
24
Rev. 0.85, 2004-04
HYS72T64000GR-5-A HYS72T64000HR-5-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-5-A HYS72T256020HR-5-A
HYS72T256220GR-5-A HYS72T256220HR-5-A
HYS72T128000GR-5-A HYS72T128000HR-5-A
HYS72T128020GR-5-A HYS72T128020HR-5-A
Organization
Label Code Jedec SPD Revision Byte# Description 59 Psi(ca) REG 60 TPLL 61 TREG / Toggle Rate 62 SPD Revision 63 Checksum of Bytes 0-62 64 JEDEC ID Code of Infineon (1) 65 JEDEC ID Code of Infineon (2) 66 JEDEC ID Code of Infineon (3) 67 JEDEC ID Code of Infineon (4) 68 JEDEC ID Code of Infineon (5) 69 JEDEC ID Code of Infineon (6) 70 JEDEC ID Code of Infineon (7) 71 JEDEC ID Code of Infineon (8) 72 Module Manufacturer Location 73 Product Type, Char 1 74 Product Type, Char 2 75 Product Type, Char 3 76 Product Type, Char 4 77 Product Type, Char 5 78 Product Type, Char 6 79 Product Type, Char 7 80 Product Type, Char 8 81 Product Type, Char 9 82 Product Type, Char 10 83 Product Type, Char 11 84 Product Type, Char 12 85 Product Type, Char 13 86 Product Type, Char 14 87 Product Type, Char 15 88 Product Type, Char 16 89 Product Type, Char 17 90 Product Type, Char 18 91 Module Revision Code
2 GByte 2 GByte x72 x72 2 Ranks (x4) 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 Rev. 1.1 HEX HEX 8C 8C 59 59 5C 5C 11 11 C3 C3 C1 C1 00 00 00 00 00 00 00 00 00 00 00 00 00 00 xx xx 37 37 32 32 54 54 32 32 35 35 36 36 30 32 32 32 30 30 47 / 48 47 / 48 52 52 35 35 41 41 20 20 20 20 20 20 20 20 20 20 0x 0x
1 GByte 1 GByte 512 MB x72 x72 x72 1 Rank (x4) 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX 8C 59 5C 11 C0 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 30 30 47 / 48 52 35 41 20 20 20 20 20 2x Rev. 1.1 HEX 8C 59 5C 11 47 C1 00 00 00 00 00 00 00 xx 37 32 54 31 32 38 30 32 30 47 / 48 52 35 41 20 20 20 20 20 2x Rev. 1.1 HEX 8C 59 5C 11 45 C1 00 00 00 00 00 00 00 xx 37 32 54 36 34 30 30 30 47 / 48 52 35 41 20 20 20 20 20 20 2x
Data Sheet Preliminary
25
Rev. 0.85, 2004-04
HYS72T64000GR-5-A HYS72T64000HR-5-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
HYS72T256020GR-5-A HYS72T256020HR-5-A
HYS72T256220GR-5-A HYS72T256220HR-5-A
HYS72T128000GR-5-A HYS72T128000HR-5-A
HYS72T128020GR-5-A HYS72T128020HR-5-A
Organization
Label Code Jedec SPD Revision Byte# Description 92 Test Program Revision Code 93 Module Manufacturing Date Year 94 Module Manufacturing Date Week 95 Module Serial Number (1) 96 Module Serial Number (2) 97 Module Serial Number (3) 98 Module Serial Number (4) 99 Not used 127
2 GByte 2 GByte x72 x72 2 Ranks (x4) 2 Ranks (x4) PC2-3200R-333 Rev. 1.1 Rev. 1.1 HEX HEX xx xx xx xx xx xx xx xx xx 00 xx xx xx xx xx 00
1 GByte 1 GByte 512 MB x72 x72 x72 1 Rank (x4) 2 Ranks (x8) 1 Rank (x8) Rev. 1.1 HEX xx xx xx xx xx xx xx 00 Rev. 1.1 HEX xx xx xx xx xx xx xx 00 Rev. 1.1 HEX xx xx xx xx xx xx xx 00
Data Sheet Preliminary
26
Rev. 0.85, 2004-04
HYS72T64000GR-5-A HYS72T64000HR-5-A
Product Type
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
7.0 Package Outline 7.1 Raw Card A Module Package DDR2 Registered DIMM Modules Raw Card A one physical rank, 9 components x8 organised
133.35 + 0.15
2.7 max.
Front View
Register PLL
30.0.
4.0
pin 1 5,175 63,0
64
65 55,0 5.0
120 5,175
1.27 + 0.1
PCB warpage 0.40
Backside View
pin 121 10.0 184 185 240
17.80
3
3
Detail of Contacts A 0.20 + 0.15 2.50 + 0.20 -
Detail of Contacts B 5.0 0.75R 3.8 typ. 1.5 2.5
0.8 + 0.05
1.0
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet Preliminary
27
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
7.2 Raw Card B
Module Package DDR2 Registered DIMM Modules Raw Card B two one physical rank, 18 components x8 organised
1 3 3.3 5 + 0.15
4.0 m a x.
Front View
Register PLL
4 .0 30.0.
p in 1 5,1 75 6 3,0
64
65 55 ,0 5.0
1 20 5 ,1 7 5
1 .27 + 0.1
PCB warpage 0.40
Backside View
pin 1 21 10.0 1 84 185 240
17.80
3
Register
3
D e ta il of C on tac ts A 0.20 + 0.15 2.50 + 0.20 -
D e tail o f C o nta cts B 5 .0 0 .75 R 3.8 typ. 1 .5 2.5
0 .8 1 .0
+ 0.05 -
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet Preliminary
28
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
7.3 Raw Card C
Module Package DDR2 Registered DIMM Modules Raw Card C one physical rank, 18 components x4 organised
1 3 3.3 5 + 0.15
4.0 m a x.
Front View
Register PLL
4 .0 30.0.
p in 1 5,1 75 6 3,0
64
65 55 ,0 5.0
1 20 5 ,1 7 5
1 .27 + 0.1
PCB warpage 0.40
Backside View
pin 1 21 10.0 1 84 185 240
17.80
3
Register
3
D e ta il of C on tac ts A 0.20 + 0.15 2.50 + 0.20 -
D e tail o f C o nta cts B 5 .0 0 .75 R 3.8 typ. 1 .5 2.5
0 .8 1 .0
+ 0.05 -
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO-237)
Data Sheet Preliminary
29
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
7.4 Raw Card (tbd)
Module Package DDR2 Registered DIMM Modules Raw Card (tbd.) two physical ranks, 36 components x4 organised - planar version
133.35 + 0.15
4.0 max.
Front View
Register PLL Register
4.0 30.0
pin 1 5,175 63,0
64
65 55,0 5.0
120 5,175
1.27 + 0.1
PCB warpage 0.40
Backside View
pin 121 10.0 184 185 240
17.80
3
3
Detail of Contacts A 0.20 + 0.15 2.50 + 0.20 -
Detail of Contacts B 5.0 0.75R 3.8 typ. 1.5 2.5
0.8 + 0.05
1.0
note: all outline dimensions and tolerances are in accordance with the JEDEC standard (MO237)
Data Sheet Preliminary
30
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
8.0 Nomenclature (Modules & Components)
8.1 DDR2 DIMM Modules
1 Example:
1 2 3
INFINEON Prefix Module Data Width DRAM Technology
2 72
3 T
4 128
5 0
6 2
7 8 9
7 0
8 G
9 R
10 -5
11 -A
0 = standard 2 = dual die package G= BGA components R = Registered DIMMs U = Unbuffered DIMMs DL = Small Outline DIMMs -5 = PC2-3200 (DDR2-400) -3.7 = PC2-4300 (DDR2-533) -3 = PC2-5400 (DDR2-667) A = 1st Generation B = 2nd Generation C = 3rd Generation
HYS
HYS for DIMM Modules 64 = Non-ECC Modules 72 = ECC Modules T = DDR2 64 = 64 Mb 128 = 128 Mb 256 = 256 Mb 0 = first generation 0 = One Rank 2 = Two Ranks
Product Variations Package Module Type
4
Memory Density per I/O
10
Speed Grade
5
Raw Card Generation Number of Memory Ranks
11
Die Revision
6
Multiplying "Memory Density per I/O" with "Module Data Width" and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall module memory density in MBytes.
8.2 DDR2 Memory Components
1 Example: HYB
2 18
3 T
4 512
5 40
6 0
7 A
8 C
9 -5
1 2
INFINEON Component Prefix Power Supply Voltage
HYB for DRAM Components 18 = 1.8 V Power Supply
6 7
Product Variations Die Revision
0 = standard 2 = dual die package A = 1st Generation B = 2nd Generation C = 3rd Generation C = BGA package F = BGA package (lead and halogen free) -5 =...DDR2-400 -3.7 =.DDR2-533 -3 =...DDR2-667
3
DRAM Technology
T = DDR2 256 = 256 Mb 512 = 512 Mb 1G = 1024Mb 40 = x4, 4 data in/outputs 80 = x8, 8 data in/outputs 16 = x16, 16 data in/outputs
8
Package Type
4
Memory Density
9
Speed Grade
5
Memory Organisation
Data Sheet Preliminary
31
Rev. 0.85, 2004-04
HYS72T[256/128/64][0/2][0/2]0[G/H]R-[5/3.7]-A Registered DDR2 SDRAM Modules
Data Sheet Preliminary
32
Rev. 0.85, 2004-04

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